1. Field of the Invention
The present invention relates generally to methods for photo-exposing photosensitive layers within integrated circuits. More particularly, the present invention relates to methods for photo-exposing photosensitive layers which bridge from low step height to high step height substrate layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. These electrical circuit elements are interconnected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
As semiconductor technology has advanced, the complexity of integrated circuits has increased in both the horizontal and vertical dimensions. In particular, with respect to complexity in the vertical dimension it is common in the art that advanced integrated circuits will often have topographic step height variations of at least one micron, over which topographic step height variations it is desired to form patterned layers, typically patterned conductor layers.
While the substantial topographic step height variations typically encountered in advanced integrated circuits are often inevitable in the design and manufacture of those advanced integrated circuits, such topographic step height variations often provide significant impediments to manufacturing those advanced integrated circuits. In particular, substantial topographic step height variations often provide significant difficulties in providing upon substrate layers exhibiting those substantial topographic step height variations patterned layers having high resolution throughout the complete topographic step height variation through which those patterned layers are desired to be patterned. These difficulties are typically based in the limited depth of focus typically achievable with advanced photolithographic exposure tooling in comparison with substantial topographic step height variations through which high resolution photo-exposure of patterned layers is desired.
The problem associated with the limited depth of focus is illustrated by reference to FIG. 1. Shown in FIG. 1 is a substrate layer 10 which has a first region R1 having a high step height plateau formed therein vertically separated from a third region R3 having a low step height plateau formed therein by a second region R2 of intermediate step height. The high step height plateau is separated from the low step height plateau by a topographic step height variation H. Formed upon the substrate layer 10 is a blanket conformal photosensitive layer 12 which is desired to be patterned with high resolution through the complete topographic step height variation H. In order to accomplish this high resolution patterning, the blanket conformal photosensitive layer 12 is preferably photo-exposed through a reticle (not shown) under exposure conditions to provide a desired Depth of Focus d-DoF which spans the topographic step height variation H. Unfortunately, the desired Depth of Focus d-DoF conditions are typically not achievable with advanced photo-exposure tooling and conventional reticles. Typically, achievable Depth of Focus a-DoF conditions are achieved, where the achievable Depth of Focus a-DoF is significantly less than either the desired Depth of Focus d-DoF or the topographic step height variation H.
The depth of focus limitations in forming high resolution patterned layers which bridge topographic step height variations from high step height to low step height substrate layers within integrated circuits are generally known as a detractor which potentially limits the heights of topographic step height variations upon which high resolution patterned conformal photosensitive layers may be formed in integrated circuits. Unfortunately, however, little is disclosed in the art regarding methods by which depth of focus limitations may be overcome in order to provide high resolution patterned conformal photosensitive layers upon high step height topography substrate layers within integrated circuits.
Thus, it is towards the goal of forming high resolution patterned conformal photosensitive layers upon high step height topography substrate layers within integrated circuits, which high resolution patterned conformal photosensitive layers maintain their high resolution throughout the differences in step height within the high step height topography substrate layers, that the present invention is directed.